Path: utzoo!attcan!uunet!aplcen!uakari.primate.wisc.edu!zaphod.mps.ohio-state.edu!wuarchive!cs.utexas.edu!asuvax!ncar!boulder!hunt From: hunt@boulder.Colorado.EDU (Lee Hunt) Newsgroups: comp.sys.next Subject: Re: SOME ADVICE FOR NEXT Message-ID: <27779@boulder.Colorado.EDU> Date: 9 Oct 90 02:56:57 GMT References: <340@atncpc.UUCP> <1990Oct8.182201.7907@ux1.cso.uiuc.edu> Sender: news@boulder.Colorado.EDU Reply-To: hunt@snoopy.Colorado.EDU (Lee Hunt) Distribution: comp Organization: University of Colorado, Boulder Lines: 24 In article <1990Oct8.182201.7907@ux1.cso.uiuc.edu> dorner@pequod.cso.uiuc.edu (Steve Dorner) writes: >In article melling@cs.psu.edu (Michael D Mellinger) writes: >>etc. I think the IBM RS/6000 can do 4 instructions in one clock >>cycle(ideally). A CPU that runs at 50MHz and completes 4 instructions >>(on average) a cycle is going to give you 200 mips. > >No, because RISC instructions do less. You have to normalize to VAX 780 >mips if you want to make "real" comparisons. > >-- >Steve Dorner, U of Illinois Computing Services Office >Internet: s-dorner@uiuc.edu UUCP: uunet!uiucuxc!uiuc.edu!s-dorner As I understand it, "RISC" in the RISC/6000 is a misnomer -- the machine is only called a RISC machine because it processes at least 1 instruction per cycle. The instruction set is quite large (~180 opcodes, I think I recall). So, in this case the instructions are as "watered down" as in the "conventional" RISC machines (although I do believe that the more complex instructions must be run serially, 1 clock cycle each). | --Lee | | Dave Haynie is Bob! | | hunt@spot.colorado.edu ...!ncar!boulder!spot!hunt |