Path: utzoo!attcan!uunet!cs.utexas.edu!sun-barr!newstop!sun!slovax!lm
From: lm@slovax.Sun.COM (Larry McVoy)
Newsgroups: comp.arch
Subject: Re: DEC RISC Architecture?
Message-ID: <143627@sun.Eng.Sun.COM>
Date: 11 Oct 90 16:54:09 GMT
References: <4462@trantor.harris-atd.com> <107038@convex.convex.com>
Sender: news@sun.Eng.Sun.COM
Reply-To: lm@sun.UUCP (Larry McVoy)
Organization: Sun Microsystems, Mountain View
Lines: 10

In article <107038@convex.convex.com> pelakh@mozart.convex.com (Boris Pelakh) writes:
>I don't know much about this new processor, but option 3 - porting VMS to RISC
>seems to be highly unlikely, considering the fact that VMS heavily
>relies on the
>original VAX architecture with it's ultra-CISC style instruction set.

I heard that this chip had a fair bit of stuff that would allow it to emulate
a VAX; both hardware and hooks for software.
---
Larry McVoy, Sun Microsystems     (415) 336-7627       ...!sun!lm or lm@sun.com