Newsgroups: comp.arch
Path: utzoo!henry
From: henry@zoo.toronto.edu (Henry Spencer)
Subject: Re: DEC RISC Architecture?
Message-ID: <1990Oct12.191024.17856@zoo.toronto.edu>
Organization: U of Toronto Zoology
References: <4462@trantor.harris-atd.com> <107038@convex.convex.com> <16034@yunexus.YorkU.CA>
Date: Fri, 12 Oct 90 19:10:24 GMT

In article <16034@yunexus.YorkU.CA> davecb@yunexus.YorkU.CA (David Collier-Brown) writes:
>  As to running VMS on a RISCy chip, it depends on the expansion factor when
>one maps (translates) VAX instructions into sequences of RISC instructions.
>It is simple to go the other way: Mips did so to simulate their earlier
>machines on a VAX. Going to a simpler architecture is a straightforward but
>**labourious** problem ...

Unfortunately, there are a couple of big jokers in the deck whenever you
are talking about emulating one machine on another.  Actual instruction
selection is not that big a deal.  The big problems with the actual
translation typically are condition codes and data formats.  (Note that
"data formats" includes things like stack frames -- do you really want
your nice fast RISC to spend half its time emulating the VAX calling
sequence?)  When talking about kernel code, another big problem will
be assumptions of atomic execution of instructions.  It Is Rumored,
to use a non-VMS example, that the NFS code Sun ships is full of
assumptions that "i++" is an atomic operation, which is true on a
single-processor 68k but not on most RISCs.
-- 
"...the i860 is a wonderful source     | Henry Spencer at U of Toronto Zoology
of thesis topics."    --Preston Briggs |  henry@zoo.toronto.edu   utzoo!henry