Path: utzoo!attcan!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!rutgers!cbmvax!jesup
From: jesup@cbmvax.commodore.com (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: 80960CA v 68040 comparative benchmark
Message-ID: <15102@cbmvax.commodore.com>
Date: 11 Oct 90 20:20:21 GMT
References: <18653.27132b53@windy.dsir.govt.nz>
Reply-To: jesup@cbmvax.commodore.com (Randell Jesup)
Organization: Commodore, West Chester, PA
Lines: 53

In article <18653.27132b53@windy.dsir.govt.nz> srghgcp@windy.dsir.govt.nz writes:
>We are in the business of designing high performance data communications
>servers, and are about to embark on new development work with FDDI. We
>have been evaluating two processors (Intel 80960CA and Motorola 68040)
>as compute engines. We currently use the 68020. We have 
>completed benchmarking the 80960CA, with the following results;

	Be careful to chose your benchmarks to reflect the sort of load that
will be put on the system.  For example, Dhrystone heavily tests a compiler's
string handling (and the string library), and some other areas are do not
contribute heavily to the result.  Cache size can cause a good showing while
having a dramatic drop in performace for a larger test (for example, pushing
and 80286 past a 64K-byte data space).

	I would advise seeing if you can find some way to benchmark some
portion of the system you expect to use, or something similar (maybe some
tcpip code, or whatever).

>DRAM runs 3-1-1-1 reads and 2-1-1-1 WS writes. The compiler does not

	Do they do this at the hypothetical 33Mhz?

>Since the hardware can handle 33MHz with no loss of performance (no more WS)
>over 25MHz, we can scale the result for 33MHz, SRAM@ level 2......29812!!!

	Scaling can be deceptive.

>For comparison we ran the same tests on a VAX and our 68020 system....
>VAX 11/780......1400. The 68020 has 1 WS DRAM, the compiler was Crosscode
>C with no optimisation (it doesn't seem to make a lot of difference anyway)
>
>68020@16.5 MHz cache on reg vars on, ............3242
>68020@16.5 MHz cache off reg vars on.............2864

	Sounds like a pretty poor C compiler.  A 14Mhz '020 should be able
to do ~4500 with a reasonable microcomputer compiler (I think that was no reg
vars), even on a running system with VBlank interrupts occurring, etc.  I'm
quite sure the 80960 has a good, state-of-the-art compiler (or at least
reasonably close).

>We are still building our 68040 system (we have a sample 25MHz 68040) but
>based on Motorolas performance figures this gives a projected figure of
>around 22000 Dhrystones. A 68040@25MHz = 5(68020@16.67MHz). This assumes 
>no optimisation, and a zero WS 68040 system.

	The relation between speeds of '030's and '040's should be more
accurate than '020's and '040's, since '030's have data caches, and had
tighter microcode.

-- 
Randell Jesup, Keeper of AmigaDos, Commodore Engineering.
{uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.cbm.commodore.com  BIX: rjesup  
Common phrase heard at Amiga Devcon '89: "It's in there!"