Path: utzoo!attcan!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!uunet!ssbell!dsndata!wayne From: wayne@dsndata.uucp (Wayne Schlitt) Newsgroups: comp.arch Subject: Re: DEC RISC Architecture? Message-ID: Date: 12 Oct 90 12:12:31 GMT References: <4462@trantor.harris-atd.com> <107038@convex.convex.com> <143627@sun.Eng.Sun.COM> Sender: wayne@dsndata.UUCP Organization: Design Data Lines: 31 In-reply-to: lm@slovax.Sun.COM's message of 11 Oct 90 16:54:09 GMT In article <143627@sun.Eng.Sun.COM> lm@slovax.Sun.COM (Larry McVoy) writes: > In article <107038@convex.convex.com> pelakh@mozart.convex.com (Boris Pelakh) writes: > >I don't know much about this new processor, but option 3 - porting VMS to RISC > >seems to be highly unlikely, considering the fact that VMS heavily > >relies on the > >original VAX architecture with it's ultra-CISC style instruction set. > > I heard that this chip had a fair bit of stuff that would allow it to emulate > a VAX; both hardware and hooks for software. is this something like what HP did when they converted their HP3000 MPE systems to the RISC based HP-PA system? i know that HP has had a painful time converting to RISC, even though they started a long time ago. the first RISC boxes didnt appear for a long time and even then, they had a hard time getting the new fast CPU to run the old code as fast as the 2-3 year old computers they replaced. I hear that recompiling your code did wonders for your performance... fortunately for HP, most of the HP3000 shops didnt use assembler or languages that did incremental compiles. thinking about it, i guess IBM has done similar things with their S/34->S/36->S/38->AS/400 line of computers. it is my understanding that all of these computers actually had very different instruction sets, but because everyone used RPG, people could move to the other computers fairly easily... -wayne