Path: utzoo!attcan!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: DEC RISC Architecture?
Message-ID: <8186@scolex.sco.COM>
Date: 14 Oct 90 09:24:12 GMT
References: <4462@trantor.harris-atd.com> <107038@convex.convex.com> <143627@sun.Eng.Sun.COM>
Sender: news@sco.COM
Reply-To: seanf (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 34


In article <143627@sun.Eng.Sun.COM> lm@sun.UUCP (Larry McVoy) writes:
>I heard that this chip had a fair bit of stuff that would allow it to emulate
>a VAX; both hardware and hooks for software.

Well... pure speculation time.

It should be possible to take the "most common instructions" and hardwire
them.  I mean instruction and operand types, that is.  For example

	mov (rx), ry

could be a valid single instruction (but a bit long, I will admit:  
3 bytes, I believe).  Then, you trap all "instructions" that you don't
recognise; for example, you could trap

	mov @(_foobar), @(_barf)

(Is that a valid VAX instruction?  I don't have my reference here, and would
probably never use such an instruction anyway 8-).)

Depending on the instruction mix, this could result in a *very* fast
processor.  If you only handle certain operand mixes, you're dealing with
(more or less) fix-lengthed instructions, so you can more easily pipeline
the sucker.

Anyway, just a thought.  Others know more than I do, obviously 8-).

-- 
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Sean Eric Fagan  | "*Never* knock on Death's door:  ring the bell and 
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