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From: schow@bcarh185.bnr.ca (Stanley T.H. Chow)
Newsgroups: comp.arch
Subject: Re: harvard architectures
Message-ID: <3468@bnr-rsc.UUCP>
Date: 16 Oct 90 16:04:34 GMT
References: <9010160322.AA13808@lilac.berkeley.edu>
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Reply-To: bcarh185!schow@bnr-rsc.UUCP (Stanley T.H. Chow)
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In article <9010160322.AA13808@lilac.berkeley.edu> rmbult01@ulkyvx.BITNET writes:
>A cursory search of some available computer architecture books
>and some indexes for information on harvard architectures did not
>yeild much.  Could anyone e-mail me some information on harvard
>architectures, particularly comparing them with non-harvard,
>implementation issues, etc.  Also, perhaps some machines which
>use(d) harvard architecture.  Any sources or bibliographies would
>be helpful.

Our telephone switches are harvard. The NT-40 processor (propietary design)
has two buses going to separate memory banks for program and data. The two
sides used the same memory cards, but was addressed in different units -
16 bit for data, 8 bit for program.

This was mostly for reliability - the program store is safe from errant
processes. Of course, this also doubles the memory bandwidth. There may
have been some papers published but I wasn't in the area at the time
(lat 70's or early 80's).

Incidentally, I have always wondered why this busing arrangement is
known as "Harvard". Anyone know?


Stanley Chow        BitNet:  schow@BNR.CA
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