Path: utzoo!attcan!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: 64 bit sparc ship sets
Message-ID: <2774@crdos1.crd.ge.COM>
Date: 18 Oct 90 15:00:03 GMT
References: <5791@munnari.oz.au>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
Lines: 20

In article <5791@munnari.oz.au> raob@mullian.ee.mu.OZ.AU (richard oxbrow) writes:

| 	[The blurb that i am currently looking at says that it has an
| 	8k cache on board (6k instruction and 2k data).]

  Okay, someone enlighten me, why that mix of cache. I would assume that
cache would be better spent on data than code, since (most) code is
pipelined and except for jumps not hurt by cache misses. However, when a
data fetch results in a cache miss, the CPU is esentially blocked
(modulo any parallelism provided).

  I preseme that there's a good reason for this which I'm missing, but
I'm fairly sure of my assumptions, having done a bit of scope and
counter work with an 8086 with slow memory and seen that the jumps were
a lot less frequent than the data fetches. Of course on an uncached
system there were lots of blocks due to data write, but that was
identified, and writes are a lot less than reads, anyway.
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
    VMS is a text-only adventure game. If you win you can use unix.