Path: utzoo!attcan!uunet!husc6!spdcc!esegue!compilers-sender From: golds@fjcnet.GOV (Rich Goldschmidt) Newsgroups: comp.compilers Subject: Re: Compilers taking advantage of architectural enhancements Summary: automating compiler generation? Keywords: design Message-ID: <1990Oct12.230424.930@esegue.segue.boston.ma.us> Date: 12 Oct 90 17:43:47 GMT References: <1990Oct9> <3300194@m.cs.uiuc.edu> Sender: compilers-sender@esegue.segue.boston.ma.us Organization: Federal Judicial Center, Washington, D.C. Lines: 16 Approved: compilers@esegue.segue.boston.ma.us [Copied from comp.arch -John] Maybe this is naive or too futuristic, but is anyone working towards methods for automatically generating a compiler based on the architecture design? It would seem that even before there is silicon, there is enough info about a new CPU in the CAD system used for layout that the features of special interest for generating a compiler are known. To the extent that generating a compiler is rule based (those tasks a good CS grad can do?), why hasn't it been automated? Or are there people working on this now? Chip designers might even take compilers into consideration in their designs :-). -- Rich Goldschmidt: uunet!fjcp60!golds or golds@fjc.gov -- Send compilers articles to compilers@esegue.segue.boston.ma.us {ima | spdcc | world}!esegue. Meta-mail to compilers-request@esegue.