Path: utzoo!attcan!uunet!world!esegue!compilers-sender From: ctl8588@rigel.tamu.edu (LAUGHLIN, CHET) Newsgroups: comp.compilers Subject: Re: Compilers taking advantage of architectural enhancements Summary: automating compiler generation? Keywords: design Message-ID: <9097@helios.TAMU.EDU> Date: 14 Oct 90 21:25:23 GMT References: <1990Oct9> <3300194@m.cs.uiuc.edu> Sender: compilers-sender@esegue.segue.boston.ma.us Reply-To: ctl8588@rigel.tamu.edu (LAUGHLIN, CHET) Organization: TAMU Lines: 18 Approved: compilers@esegue.segue.boston.ma.us In article <1990Oct12.230424.930@esegue.segue.boston.ma.us>, golds@fjcnet.GOV (Rich Goldschmidt) writes... >Maybe this is naive or too futuristic, but is anyone working towards >methods for automatically generating a compiler based on the architecture >design? It would seem that even before there is silicon, there is I would suggest "Computer Architecture a Quantitative Approach" by John L Hennessy and David A Patterson, Morgan Kaufmann Publishers, c1990. They speak at several different points on how HLL compilers will affect the system performance. In addition, they mention some common pitfalls designers tend to not think about till after the fact...like KISS for instruction sets because compiler writers deal with a simple principle of "make the common fast and the rest correct." (Of course, they are biased by background...but the book has many good points) Chet Laughlin CTL8588@RIGEL.TAMU.EDU (128.194.4.4) -- Send compilers articles to compilers@esegue.segue.boston.ma.us {ima | spdcc | world}!esegue. Meta-mail to compilers-request@esegue.