Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!zaphod.mps.ohio-state.edu!rpi!clarkson!news.clarkson.edu!nelson From: nelson@sun.soe.clarkson.edu (Russ Nelson) Newsgroups: comp.dcom.lans Subject: Re: Intel 82583 Ethernet chip Message-ID: Date: 13 Oct 90 03:03:26 GMT References: <1990Oct12.153422.20325@watdragon.waterloo.edu> Sender: news@news.clarkson.edu Reply-To: nelson@clutx.clarkson.edu (aka NELSON@CLUTX.BITNET) Distribution: na Organization: Clarkson University, Potsdam NY Lines: 28 In-Reply-To: jcsmirnios@spurge.uwaterloo.ca's message of 12 Oct 90 15:34:22 GMT Nntp-Posting-Host: image.soe.clarkson.edu In article <1990Oct12.153422.20325@watdragon.waterloo.edu> jcsmirnios@spurge.uwaterloo.ca (John C. Smirnios) writes: I need some information on Intel's 82583 Ethernet LAN chip (used on 3COM 505, 507 and 523/MC cards). Those Ethernet cards use the 82586. I have the data sheets on it from the 1988 Microcommunications Handbook, but they aren't complete. In particular, the data I have does not describe the structure of the Initialization Root. Other than that it seems quite complete. What's an Initialization Root? I've got Intel's "LAN Component User's Manual", which thoroughly documents the 82586, and I see no reference to any initialization root. Does anyone out there know the structure of the root? It might help me to know where you got it, too. The document I'm looking at is order number 230814-002. Also be aware that the 82586 has bugs ("errata"), and if you don't program with a bug list in hand, your software will eventually be run on a machine that has the bugs, and boom!. The current revision of the chip is the D step, so when you get the documentation, insist on a D step errata sheet. -- --russ (nelson@clutx [.bitnet | .clarkson.edu]) Russ.Nelson@$315.268.6667 It's better to get mugged than to live a life of fear -- Freeman Dyson