Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!convex!swarren From: swarren@convex.com (Steve Warren) Newsgroups: comp.sys.amiga.hardware Subject: Re: Bank switched CHIP RAM? (Re: 24 Bit Video ..) Keywords: Off the wall idea? Message-ID: <107062@convex.convex.com> Date: 11 Oct 90 14:46:43 GMT References: <1990Oct3.194556.7031@lth.se> <106878@convex.convex.com> <489@cbmger.UUCP> Sender: news@convex.com Organization: Convex Computer Corporation, Richardson, Tx. Lines: 79 In article <489@cbmger.UUCP> peterk@cbmger.UUCP (Peter Kittel GERMANY) writes: >In article <106878@convex.convex.com> swarren@convex.com (Steve Warren) writes: >>The solution to the bandwidth problem is banks. We already have two >>seperate banks of chip mem in the 3000 with 2 Megs of chip. The trick >>is to set it up so that as long as the video DMA is accessing one of the two >>banks, the CPU can have transparent access to the other bank simultaneously >>(ie no cycle-stealing necessary). > >Crap. (Sorry) But PLEASE understand that Chip RAM in an Amiga is not solely >used for video! There are many many other important data held there. Second >caveat is that you would lose the big advantage of arbitrarily placeable >bitmaps in memory, you would be forced to arrange them properly across >your banks. And what happens with our system or sound data during a bank >switch? Peter, I have had my Amiga since 1985 ;^). You have missed the point. I am not talking about "bank-swapping" ala Apple ][. All the memory is always there. These banks do not share the same physical addresses. On either side of the memory system there is no appearance of any difference in the location of data. You write data to the same location as always, and any time you read that data, it is always available at the same address - same data, unless the other processor has modified the data. At no time does one bank supersede the other or present alternate data in the same location. All chip memory continues to appear as continuous addresses as before. The devices accessing it will have no way of knowing that some of the data came from bank A, while some of the data came from bank B. It is only a function of the address mapping. The only purpose of the banks is to allow you to double your bandwidth without increasing the speed of your memory chips, by allowing simultaneous access to the memory by two processors, as long as they do not both make requests to the same bank. This is a standard technique utilized in multiprocessor systems like CONVEXen (see header), of which the Amiga is an example (although not a general multiprocessor machine). The technique can be applied and will improve bandwidth much more cheaply than trying to make the memory chips go faster. In order to implement this you must have a 2-way crossbar switch that would be controlled by Agnus or a relative of Agnus. On one processor port of the crossbar you have the CPU and related devices (harddrives, etc). On the second processor port you have the address-limited devices (all custom-chip accesses that are limited to *only* chip mem). I have referred to all these devices collectively (and erroneously - but I was just trying to be succinct) as "the graphics processor". Understand that by this term I actually mean all the chip-mem limited devices. On the other side of the crossbar switch you have bank A chip-mem and bank B chip-mem connected to the two memory ports of the crossbar switch. Now the graphics processor has to have preemptive access to chip-mem (no waiting allowed). Therefore the CPU must synchronize with the graphics processor so that arbitration will always give a bank in contention to the graphics processor. The CPU may not be granted access to bank B while the graphics processor is in the middle of a bus cycle in bank A. But the CPU may be allowed access to bank B at the *start* of a bus cycle in which the graphics processor is accessing bank A. In addition, the CPU of course could access either bank at the start of a cycle in which the graphics processor makes no requests. Of course the assumption is that the graphics processor is now so hungry that this will rarely be the case. That is why the CPU needs its own independent port into chip-mem. Otherwise the CPU rarely gets access (in this hypothetical system with higher resolution). I am sorry if my original post was confusing because I did not include enough details. My own job is involved in the development of multi-bank/ multi-port interleaved memory systems, so I sometimes take these ideas for granted. Feel free to poke holes in this concept; just make sure that it is really what I am talking about ;^). Regards, -- _. --Steve ._||__ DISCLAIMER: All opinions are my own. Warren v\ *| ---------------------------------------------- V {uunet,sun}!convex!swarren; swarren@convex.COM