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From: wille@frith.msu.edu (Jeffrey Wille)
Newsgroups: comp.sys.amiga.hardware
Subject: CIA timing specs
Message-ID: <1990Oct17.023324.21682@msuinfo.cl.msu.edu>
Date: 17 Oct 90 02:33:24 GMT
Sender: news@msuinfo.cl.msu.edu
Distribution: usa
Organization: Michigan State University, College of Engineering
Lines: 12

I am posting this for my brother, who does not have access to the net.

He is building a project that connects to the parallel port of his A500.  
He needs to know one timing spec for the CIA chip, if someone could be
so gracious as to tell him :-).  When data is input from the parallel port,
for how long does DS go low?  He has a 7 MHz 68000, if you need that.
Please respond to rbw@spock.byu.edu.  Thanks.

				Jeff Wille (wille@frith.egr.msu.edu)
					   (wille@happy.egr.msu.edu)

Torture numbers, and they'll confess to anything.   -- Gregg Easterbrook