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From: jeh@sisd.kodak.com (Ed Hanway)
Newsgroups: comp.sys.amiga.tech,comp.sys.amiga.hardware
Subject: Re: Possible E-Clock fixes
Message-ID: <1990Oct12.124753.14723@sisd.kodak.com>
Date: 12 Oct 90 12:47:53 GMT
References: <1990Oct11.193142.13719@ecst.csuchico.edu>
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mrush@csuchico.edu writes:
>
>  I was (as many people do) looking over the infamous 14Mhz hack for
>the Amiga and was wondering about the possibility of the following solution
>to the E-Clock problem.
>
>  Since the mod requires the acquisition of a 14Mhz CPU, you're obviously
>going to have an extra 7Mhz CPU sitting around.
>  Would it be possible to take that 7Mhz part, hook up the supply voltages,
>7Mhz input clock (and maybe a couple other things), and then run the E-Clock
>from that CPU into the Amiga's E-Clock input (leaving everything else
>unconnected).

(First disclaimer: It's been a few years since I looked at this.)

Generating an E clock from a 7MHz clock is as easy as building a divide-by-10
circuit.  That will get the proper frequency and duty cycle.  This can be
done with one cheap 74xx9something chip; no need to use a whole 68000 for that.

The real problem is that the E clock is used internally by the 68000, in
combination with VMA and VPA, for synchronous bus cycles.

A little background:  Normally, the 68000 uses asynchronous bus cycles; that is,
it waits until it receives DTACK to end the bus cycle.  Because DTACK is
generated by the peripheral (e.g. a memory controller), this means that, in
theory, the CPU could run as fast as it wants, but as long as it waits for
DTACK, it will work with memory or I/O of any speed.

However, the 68000 can also run synchronous bus cycles which end on an edge of
the E clock.  Obviously, if you speed up the CPU, that speeds up the E clock,
and that makes the synchronous cycles run faster, but only if the peripherals
which use synchronous cycles can run that fast.  In the Amiga, the 8520's
use sychronous cycles and are not spec'd to run much faster than 7MHz,
certainly not 14MHz.
 
A peripheral signals to the 68000 that it wants to use a synchronous cycle
by asserting VMA or VPA as soon as it is decoded.  When the 68000 detects
one of these, it will end the cycle on the next transition of the E clock
_without receiving any DTACK signal_.  The problem with generating the E
clock externally is that the 68000 is still using its internal one, which will
be completely out of sync.

Here's what I think should work:

	1) Use a divide-by-10 to generate the proper E-clock from the 7MHz
	   clock.

	2) Add external circuitry to detect VMA or VPA and generate a DTACK
	   properly synchronized with the E-clock generated in step 1.

What this should do is make every bus cycle look asynchronous to the 68000.

For a few days in 1987 a friend and I played with this idea, eventually
cramming all of the circuitry into a tiny daughterboard that contained a
16MHz oscillator, a fast 68000, and one PAL.

(Second disclaimer: I never did get this to work properly.  I noticed an
earlier message on this topic mentioned that it was necessary to synchronize
the AS signal with the 7MHz clock.  Perhaps that would work.)

Ed Hanway
uunet!sisd!jeh