Path: utzoo!attcan!uunet!world!decwrl!ucbvax!pasteur!cory.Berkeley.EDU!navas
From: navas@cory.Berkeley.EDU (David C. Navas)
Newsgroups: comp.sys.amiga.tech
Subject: Re: [-] CHIP RAM Speed Problems
Message-ID: <28741@pasteur.Berkeley.EDU>
Date: 13 Oct 90 02:21:15 GMT
References: <1990Oct9.042900.8479@IRO.UMontreal.CA>
Sender: news@pasteur.Berkeley.EDU
Reply-To: navas@cory.Berkeley.EDU
Lines: 16


In article <1990Oct9.042900.8479@IRO.UMontreal.CA> martin@IRO.UMontreal.CA (Daniel Martin) writes:
>
>   I tested the speed of an A3000/25 MHz + Aztec v3.6 with the dhrystone v2.1 
>
>   Why is there such a speed decrease (more than 3x)?

Correct me if I'm wrong, but I thought that you had to synchronize with the
CHIP memory for every access request....  That might explain it.
[CHIP RAM accessed by chip memory at 7Mhz, and while the A3000 looks at that
 memory as 32 bit, I thought it could only look at it at that speed?]

or it could be bad luck.  :)

David Navas                                   navas@sim.berkeley.edu
"Excuse my ignorance, but I've been run over by my train of thought."  -me