Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!oakhill!motaus!phil
From: phil@motaus.sps.mot.com (Phil Brownfield)
Newsgroups: comp.sys.m68k
Subject: Re: 68020 Instr Cache
Summary: Really 68030 Data Cache
Message-ID: <1990Oct15.145619.18065@motaus.sps.mot.com>
Date: 15 Oct 90 14:56:19 GMT
References: <1990Oct9.184632.18064@ariel.unm.edu> <9089@mcdcup.UUCP> <15052@cbmvax.commodore.com>
Organization: Motorola Semiconductor, Austin
Lines: 23

In article <15052@cbmvax.commodore.com> bryce@cbmvax.commodore.com (Bryce Nesbitt) writes:
>
>For a 68030, dynamic use of the cache is standard.  I/O registers 
>assert CIIN (cache inhibit in) to prevent read data from getting cached.
>
>The 68030 has a problem, however, with writes in WA mode.  Longword writes
>to longword aligned addresses allocate a valid entry in the data cache even
>if the hardware asserts CIIN.  Without an MMU you are screwed.

Are you avoiding the MMU because you don't need address translations?
Describe your I/O space as cache inhibited with a Transparent Translation
register.  The TTx registers still function while address translations
are disabled.  See 030 User's Manual sections 9.3 and 9.7.3.

>Could a system play a game with CDIS to work around the above problem?

The difficulty with CDIS is that its timings are not specified with
respect to bus cycles.
--
Phil Brownfield
phil@motaus.sps.mot.com
{cs.utexas.edu!oakhill, mcdchg}!motaus!phil
Speaking for myself, not my employer