Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!cbmvax!valentin
From: valentin@cbmvax.commodore.com (Valentin Pepelea)
Newsgroups: comp.sys.m68k
Subject: Re: 68020 Instr Cache
Message-ID: <15202@cbmvax.commodore.com>
Date: 17 Oct 90 03:14:05 GMT
References: <1990Oct9.184632.18064@ariel.unm.edu> <9089@mcdcup.UUCP> <15052@cbmvax.commodore.com> <1990Oct15.145619.18065@motaus.sps.mot.com>
Reply-To: valentin@cbmvax.commodore.com (Valentin Pepelea)
Organization: Commodore, West Chester, PA
Lines: 23

In article <1990Oct15.145619.18065@motaus.sps.mot.com> phil@motaus.sps.mot.com
(Phil Brownfield) writes:
>
> Are you avoiding the MMU because you don't need address translations?
> Describe your I/O space as cache inhibited with a Transparent Translation
> register.  The TTx registers still function while address translations
> are disabled.  See 030 User's Manual sections 9.3 and 9.7.3.

The I/O space on our computers, the Amiga series - all models, is located
in the upper portion of the lower 16 Meg. Within that 16 Meg space, the first
2 megabytes are used by CHIP ram, memory accessible by the graphics
coprocessors. We want that part cache inhibited. The top megabyte is reserved
as ROM space. That part we want cached. I/O space is located around B000000,
while most of the rest is inhabited by extra RAM cards and I/O cards.

So the use of the TTx registers would not help at all.

Valentin
-- 
The Goddess of democracy? "The tyrants    Name:    Valentin Pepelea
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