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From: ok@goanna.cs.rmit.oz.au (Richard A. O'Keefe)
Newsgroups: comp.arch
Subject: Re: PR1ME 32I mode (was Re: Porting OSes (was DEC RISC Architecture))
Message-ID: <4016@goanna.cs.rmit.oz.au>
Date: 19 Oct 90 02:13:26 GMT
References: <3970@goanna.cs.rmit.oz.au> <1360005@aspen.IAG.HP.COM>
Organization: Comp Sci, RMIT, Melbourne, Australia
Lines: 30

In article <1360005@aspen.IAG.HP.COM>, mhjohn@aspen.IAG.HP.COM (Mark H Johnson) writes:
> / aspen:comp.arch / pcg@cs.aber.ac.uk (Piercarlo Grandi) /  8:20 am  Oct 16, 1990 /
> On 15 Oct 90 02:10:47 GMT, ok@goanna.cs.rmit.oz.au (Richard A. O'Keefe) said:

> >Maybe. But it was never supported...

Careful with those attributions.  I did *not* write that bit.

> ok> I'm sure that PR1ME's architects were overjoyed to have a chance of
> ok> getting the taste of 32V out of their mouths...

That bit I *did* write, and

> Actually 64V.

I not only should have known better, I *did* know better.  Stupid mistake.

> The compiler folks didn't much like either instruction set.

> Yes, see above.  For even more fun, you should have seen the compatible 
> RISC instruction set we put together...and did not build.

I'm puzzled.  What was the "compatible RISC instruction set" compatible
with?  Not having had the chance to use 32I mode on a P400, I came away
with the impression that 32I mode was pretty regular.  What difference
did the RISC mode make?  More registers?...  Was there anything more to
not building it than looking at cost (of writing new compilers &c)/
benefit and deciding it wasn't worth while?
-- 
Fear most of all to be in error.	-- Kierkegaard, quoting Socrates.