Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!apple!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: 64 bit sparc ship sets Message-ID: <42239@mips.mips.COM> Date: 19 Oct 90 15:50:22 GMT References: <5791@munnari.oz.au> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 25 In article <5791@munnari.oz.au> raob@mullian.ee.mu.OZ.AU (richard oxbrow) writes: > > > Does somebody have some detailed information about the > 64bit sparc chips that they might like to post. > > More specifically the > > Matsushita MN10501 (?) 64 bit sparc cpu with fpu,mmu and cache. > > [The blurb that i am currently looking at says that it has an > 8k cache on board (6k instruction and 2k data).] NOTE: to avoid confusion, this is a 32-bit architecture with 64-bit busses, i.e., like the i860. As Hennessy suggests, calling these 64-bit architectures just confuses everybody, and is completely inconsistent with past practice. I saw a a SPECmark of 12 quoted for the workstation, 1.7 MFLOPS. Can anybody confirm that, and for SPEC, give the 10 numbers? -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086