Path: utzoo!attcan!uunet!mcsun!tuvie!vmars!hp From: hp@vmars.tuwien.ac.at (Peter Holzer) Newsgroups: comp.arch Subject: Re: 64 bit sparc ship sets Message-ID: <1923@tuvie> Date: 25 Oct 90 14:08:21 GMT References: <5791@munnari.oz.au> <2774@crdos1.crd.ge.COM> Sender: news@tuvie Lines: 33 turner@sp1.csrd.uiuc.edu (Steve Turner) writes: >> (richard oxbrow) writes: >> >> | [The blurb that i am currently looking at says that it has an >> | 8k cache on board (6k instruction and 2k data).] >I'll stick my neck out and speculate as to a possible rationale for >the sizes. I assume you mean the sizes above. [stuff deleted] >In other >words, past a certain point, you don't get much "bang-for-the-buck" >out of increasing I-cache size. >D-cache on the other hand can see almost linear increase in hit rate >with increasing size (you can almost feel the breeze from my waving >hands at this point) up to quite large sizes. >SO: for small (i.e, on-chip) cache systems, you're better off >spending most of the real-estate on D- rather than I-cache. But on the chip in question the I-cache is larger than the D-cache. You just explained why it should be the other way. -- | _ | Peter J. Holzer | Think of it | | |_|_) | Technical University Vienna | as evolution | | | | | Dept. for Real-Time Systems | in action! | | __/ | hp@vmars.tuwien.ac.at | Tony Rand |