Path: utzoo!attcan!uunet!lll-winken!sun-barr!newstop!exodus!cortex.Eng.Sun.COM!rtrauben From: rtrauben@cortex.Eng.Sun.COM (Richard Trauben) Newsgroups: comp.arch Subject: Re: 64 bit sparc ship sets Message-ID: <1702@exodus.Eng.Sun.COM> Date: 25 Oct 90 15:05:34 GMT References: <5791@munnari.oz.au> <2774@crdos1.crd.ge.COM> Sender: news@exodus.Eng.Sun.COM Organization: Sun Microsystems, Mt. View, Ca. Lines: 29 In article (Steve Turner) writes: >> | [The blurb that i am currently looking at says that it has an >> | 8k cache on board (6k instruction and 2k data).] >> >> Okay, someone enlighten me, why that mix of cache. > >I'm not sure about the comment about how performance is not hurt by >I-cache misses as much as D-cache. I see the point, but jumps that >stall the pipeline are still a big performance loss. In any event I >think this is highly debatable for the general case. > >I'll stick my neck out and speculate ... I-cache .. captures most >loops, but not whole threads. ... .... about the relative sizes of the I$ to D$ on the Solbourne/Matsushita SPARC processor: i dont work for solbourne/matsushita (or play one on TV) but.. i have another theory: yes. it is true that d$ miss rates are much higher than i$ miss rates for split caches of uniform size. there are a whole lot of "typical" applications with the following statistics: 1 data memory reference for every 4 instructions. This means that data memory references only contribute 20 of the memory bandwidth bottleneck and are therefore instruction memory references are 4 times more expensive than a data memory access which misses. Equalizing the miss rate for i$ and d$ would therefore contribute to an unbalanced machine. Your mileage may vary. -Richard Trauben Sun Microsystems