Path: utzoo!attcan!uunet!know!zaphod.mps.ohio-state.edu!wuarchive!uwm.edu!ux1.cso.uiuc.edu!csrd.uiuc.edu!s4.csrd.uiuc.edu!turner
From: turner@sp1.csrd.uiuc.edu (Steve Turner)
Newsgroups: comp.arch
Subject: Re: 64 bit sparc ship sets
Message-ID: <TURNER.90Oct25154626@sp1.csrd.uiuc.edu>
Date: 25 Oct 90 20:46:25 GMT
References: <5791@munnari.oz.au> <2774@crdos1.crd.ge.COM>
	<TURNER.90Oct23173718@sp1.csrd.uiuc.edu> <1923@tuvie>
Sender: news@csrd.uiuc.edu (news)
Reply-To: turner@csrd.uiuc.edu (Steve Turner)
Organization: Center for Supercomputing R & D
Lines: 25
In-Reply-To: hp@vmars.tuwien.ac.at's message of 25 Oct 90 14:08:21 GMT

In article <1923@tuvie> hp@vmars.tuwien.ac.at (Peter Holzer) writes:
> 
> turner@sp1.csrd.uiuc.edu (Steve Turner) writes:
			...  Was this really me??  Damn.

> [stuff deleted]
> 
>>SO:  for small (i.e, on-chip) cache systems, you're better off
>>spending most of the real-estate on D- rather than I-cache.
> 
> But on the chip in question the I-cache is larger than the D-cache.
> You just explained why it should be the other way.

Right.  A typo at the end (I _meant_ "I- rather than D-", of course),
and I blow my whole argument.  Sheesh...

--
    Steve Turner (on the Si prairie  - UIUC CSRD)

    ARPANET:  turner@csrd.uiuc.edu
    Phone:    (217) 244-7293 or (217) 367-0882

    I went walking in the wasted city / Started thinking about entropy
    Smelled the wind from the ruined river / Went home to watch TV
                                                 -- Warren Zevon