Path: utzoo!attcan!uunet!zaphod.mps.ohio-state.edu!rpi!batcomputer!riley
From: riley@batcomputer.tn.cornell.edu (Daniel S. Riley)
Newsgroups: comp.sys.amiga
Subject: Re: board<>3000 RETRACTION-NEAT NEWSGROUP
Message-ID: <1990Oct22.003343.8822@batcomputer.tn.cornell.edu>
Date: 22 Oct 90 00:33:43 GMT
References: <2139@lpami.wimsey.bc.ca>
Organization: Cornell Theory Center
Lines: 23

In article <2139@lpami.wimsey.bc.ca> lphillips@lpami.wimsey.bc.ca (Larry Phillips) writes:
>Nope... It was promoted as having the ability to place multiple PICs in ONE
>expansion chassis _OR_ to place one PIC on the expansion bus. Look at the
>earliest expansion docs. External circuitry was always required to properly
>arbitrate the autoconfig operation.

Minor nit--I've got the Feb. 4 1986 expansion docs in front of me, and,
at that time, Commodore thought that two expansion backplanes with
multiple PICs *might* be possible.  There are big warnings saying that
Commodore has only tested one backplane, and the timing might not work,
and all the illustrated backplanes have buffers, and collision avoidance
and bus arbitration circuitry.

Going further back, the Nov. 25 1985 doc does mention the possibility of
passing the "bus (buffered) out in daisy chain fashion."  My impression
is that the timing doesn't work out if you buffer the bus, and the noise
gets you if you pass the unbuffered bus, so the idea was eventually
abandonded.  *HOWEVER*, none of this excuses the vast majority of SOTS
boxes with *unbuffered* pass throughs--something C-A never even implied
should work.

-Dan Riley (riley@theory.tn.cornell.edu, cornell!batcomputer!riley)
-Wilson Lab, Cornell University