Path: utzoo!attcan!uunet!ogicse!cs.uoregon.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.sys.m88k Subject: Re: 88k Macintoshes? / New 88k family member Message-ID: <42311@mips.mips.COM> Date: 23 Oct 90 03:13:57 GMT References: <1990Oct22.021837.26420@dg-rtp.dg.com> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 61 In article <1990Oct22.021837.26420@dg-rtp.dg.com> rice@dg-rtp.dg.com writes: >I've typed in a few interesting excerpts from an article >in the October 15, 1990, "Computerworld." ..... >"At last week's Microprocessor Forum technical conference >in Burlingame, Calif., Motorola described plans to introduce >a second-generation RISC chip, due out next year. Dubbed >the 88110, the microprocessor is expected to...combine >the CPU, cache memory and memory management sections on >a single chip." Now, in the "don't believe everything you read" column: I was there, and what I heard was: a) The speaker (Keith Diefendorff), and the foils, said "The following is not a product announcement but rather a disclosure of Motorola's plans for the 88000 Family and a sneak preview of the next generation processor." b) No dates were given in the talk. c) In the questions, Keith was asked "when?" and (I'm pretty sure) he said that the product would be ANNOUNCED next year. Then there was some more questioning along lines of announce-deliver intervals that I didn't catch, but I'm pretty sure Keith did NOT say it would be delivered next year. (I don't think he said it WOULDN'T BE, either.) IF SOMEBODY ELSE (WHO WAS ACTUALLY THERE) CAN CORRECT THIS, please do. Of course, this turned into "due out next year", whatever THAT means :-) >End of excerpts. It's a pretty non-technical news article; >its other salient points are the performance projections >for the new-generation 88k (50-85 MIPS) and a remark about >the fact that 88k Mac software would not be binary-compatible >with previous software. The foils say 3-5X performance increase over 88100/88200, using 0.8micron TLM HCMOS, less than 1.5M transistors. Especially interesting are the "80-bit wide internal data paths" (For FP), and other features mentioned include: runtime reordering of loads&stores, speculative execution, bus snooping w/separate tags, branch acceleration. Predictions for 2H 90's said: "4X performance increase each generation 100 million transistors 300MHz Multiple processors on a single chip 4000+ MIPS per chip within the next ten years" Summary said: "The 90's is the decade of RISC The 88000 is the strongest RISC architecture available The 88110 will set new price/performance standards Common architecture from "toaster to supercomputer" The U.S.'s largest semiconductor manufacturer is committed to RISC and to the 88000 Family" -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086