Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!oakhill!billm
From: billm@oakhill.UUCP (Bill Moyer)
Newsgroups: comp.sys.m88k
Subject: Re: New 88110 using Triple Level Metal, Highspeed CMOS
Message-ID: <4072@scorpio.oakhill.UUCP>
Date: 23 Oct 90 18:00:32 GMT
References: <42312@mips.mips.COM>
Reply-To: billm@scorpio.UUCP (Bill Moyer)
Organization: Motorola Inc., Austin, Texas
Lines: 44

In article <42312@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>I for one am willing to bet $0.75, or the price of a 12oz. Coke Classic
>(whichever amount is larger :-), that on the day when the 88110 die
>photo is officially released, the chip will NOT have triple level metel
>HCMOS processing.  Another 75cents says that on the day when the 88110
>die photo is officially released, Motorola will not be building _any_
>of its 32-bit microprocessors, RISC or CISC, 88k or 68k, using triple
>level metal CMOS processing.  I'll also bet 50 cents that the first
>merchant RISC microprocessor using CMOS transistors and triple level
>metal processing, will be from Texas Instruments.  There's already been
>a Hewlett Packard Precision RISC in TLM CMOS; if that counts as merchant
>then I've already lost the 50 cents (to myself :-).
>
>Finally, I'll stretch my resources to the limit and bet a whopping
>15 cents that when you run 100x100 DP Linpack on a system using the
>88110 (say, a future Aviion), the results will not be bit-for-bit
>identical with the previous 88100-based systems (say, the current
>Aviion).
> -- Mark Johnson	
> 	MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
>	(408) 524-8308    mark@mips.com  {or ...!decwrl!mips!mark}






you're on for the first two bets. I won't comment on the third.

As for the fourth, IEEE compliance means just that. 
I'm willing to bet that bit identical results will 
not be guaranteed with any given chip/system
(R2000/3000,SPARC,88K) if the compiler is allowed to 
reorder code for optimization purposes.







Bill Moyer
Motorola, Inc.
...!oakhill!billm