Path: utzoo!attcan!uunet!wuarchive!cs.utexas.edu!romp!auschs!awdprime!adagio.austin.ibm.com!sdl From: sdl@adagio.austin.ibm.com (Stephen Linam) Newsgroups: comp.unix.aix Subject: Re: Why 256? Message-ID: <4026@awdprime.UUCP> Date: 25 Oct 90 16:46:22 GMT References: Sender: news@awdprime.UUCP Reply-To: sdl@adagio.austin.ibm.com Organization: AIX Base Operating System Development Lines: 27 In article , bglenden@mandrill.cv.nrao.edu (Brian Glendenning) writes: |> |> I've just been reading the document "IBM RISC SYSTEM/6000 PERFORMANCE |> TUNING FOR NUMERICALLY INTENSIVE FORTRAN AND C PROGRAMS" (hey - would |> I invent all those caps!). Very nice. |> |> The only thing I think I don't understand is the tuning summary entry |> that says "Make sure leading dimension of arrays is not a multiple of |> 2 greater than or equal to 256." |> |> I first thought this had to do with cases where you had to stride |> through the array in other than the first dimension and the fact that |> you would have increased cache misses, but I can't see why the number |> "256" is picked on. Bits 18-24 (I think) of the virtual address control which entry in the cache is used for a particular address. If you are accessing data which is 256, 512, 1028 etc. double words apart, you are reducing the effective size of the cache, causing more frequent cache misses. The document you refer to mentions the pathological case, 16k bytes or 2048 double words, where the cache is effectively only 4 lines (512 bytes). -------------------------------------------------------------------- Stephen Linam AWD Austin T/L: 793-3674 Bell-net: (512) 832-3674 IBM Internet: sdl@adagio.austin.ibm.com VNET: LINAM at AUSTIN UUCP: ...!cs.utexas.edu:ibmchs!auschs!adagio.austin.ibm.com!sdl