Newsgroups: sci.electronics
Path: utzoo!utgpu!cunews!bnrgate!bwdlh131!mleech
From: mleech@bwdlh131.bnr.ca (Marcus Leech)
Subject: DPLL design needed
Message-ID: <1990Oct18.203839.20608@bnrgate.bnr.ca>
Keywords: DPLL phase-locked loops NRZI
Sender: news@bnrgate.bnr.ca (USENET News System)
Reply-To: mleech@bwdlh131.bnr.ca (Marcus Leech)
Organization: Bell-Northern Research
Date: Thu, 18 Oct 90 20:38:39 GMT

I need a DPLL design based on the PAL16R8 that can take a NRZI signal
  at 1200baud, a clock at 8 or 16 x 1200baud, and generate a
  DPLL-LOCKED signal (what this amounts to is a digital DCD).
  I'm guessing that there's a reasonably good freeware library of
  PAL equations that might contain something like this.


-----------------
Marcus Leech, 4Y11             Bell-Northern Research  |opinions expressed
mleech@bnr.ca                  P.O. Box 3511, Stn. C   |are my own, and not
VE3MDL@VE3JF.ON.CAN.NA         Ottawa, ON, CANADA      |necessarily BNRs