Path: utzoo!attcan!uunet!comp.vuw.ac.nz!windy!gpwd!gpwrdcs
From: don@gp.govt.nz
Newsgroups: comp.arch
Subject: Re: PUSH on i8088/i80x86
Message-ID: <1089.25b7ae4d@gp.govt.nz>
Date: 28 Oct 90 03:12:56 GMT
References: <1261570140@<182DAVISTD@MSU> > <208300005@prism> <1990Jan15.064658.1816@waikato.ac.nz>
Organization: Government Printing Office, Wellington, New Zealand
Lines: 31

In article <1990Jan15.064658.1816@waikato.ac.nz>, ldo@waikato.ac.nz (Lawrence D'Oliveiro) writes:
> This problem with pre/post-decrementing of SP in the Intel CPUs--
> there's another chip family with this quirk too. The analogous
> sequence
> 
> 	mov	sp, -(sp)
> 
> is supposed to give different results on different members of
> the PDP-11 family. I may be wrong (it's been a while since I've
> programmed a PDP-11) but the behaviour might occur if you replace
> SP with any of the other registers, as well.
> 
> Anybody else remember this? Or am I just showing my age?

Yup, and yes, it does affect all registers (did you expect otherwise? SP
is just another name for R6 after all).  According to my Microcomputer
Processor Handbook (deals with LSI-11 processors), on the LSI-11/23,
PDP-11/15, 11/20, 11/35 & 11/40, an instruction along the lines of MOV
Rn, (Rn)+ or MOV Rn, -(Rn) results in Rn being incremented or decremented
before being used as the source operand, whereas on the LSI-11,
PDP-11/04, 11/05, 11/10, 11/34 and 11/45 (that's all this book, circa
1979, mentions), the initial contents of the source operand are used. 
The same goes for things like MOV Rn, @(Rn)+. 

There are quite a large number of differences between different PDP-11 
models - the table of differences runs to 12 pages.

Don Stokes  ZL2TNM    /  /                               vuwcomp!windy!gpwd!don
Systems Programmer   /GP/ Government Printing Office <-- until 31-Jan-1990
__(and_Postmaster)__/  /__Wellington__New_Zealand________don@gp.govt.nz________
The number of errors is proportional to the number of people watching.