Path: utzoo!attcan!uunet!wuarchive!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: R3000A question ??? Message-ID: <42474@mips.mips.COM> Date: 29 Oct 90 18:26:26 GMT References: <14900018@hpdmd48.boi.hp.com> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 26 In article <14900018@hpdmd48.boi.hp.com> sritacco@hpdmd48.boi.hp.com (Steve Ritacco) writes: >As I understand it, the Mips R3000A has been released. >Would someone mind explaining the "dynamic byte swapping" feature? In R2000s and R3000s, when you reset the CPU, you choose at that time which byte-order is to be used, and it doesn't change without another reset. It is possible (and has been done), to use external circuits, plus software, to have a "soft reset" that can flip the whole machine. R6000s, and R3000As have a "RE" (Reverse Endian) status bit, in addition, part of the coprocessor 0 status register. If the kernel sets this bit, its own execution is unaffected, but if it transfers to user state with the bit set, the user process runs in the Reverse byte order compared to the kernel. There is, of course, a way to distinguish Big-Endian binaries from Little-Endian ones (magic number), and hence, the hardware is there to let a single machine run a mixture of such binaries, i.e., the byte order is selected on a process-by-process basis. (Note that this is NOT a product announcement, or commitment that anyone is going to do the software work ("a minor matter of software" :-) just a note that the hardware now permits this in a sensible fashion.) -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086