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From: alan@uf.msc.umn.edu (Alan Klietz)
Newsgroups: comp.arch
Subject: Re: i860 MFLOP rate?
Message-ID: <2859@uc.msc.umn.edu>
Date: 30 Oct 90 21:51:34 GMT
References: <9010291839.AA07178@lilac.berkeley.edu> <1845@exodus.Eng.Sun.COM>
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Reply-To: alan@uf.UUCP (Alan Klietz)
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rmbult01@ulkyvx.BITNET (Robert M. Bultman) writes:
<The i860 has been quoted as having a peak MFLOP rate of ~150
<MFLOPS.  (This is more of a guess.)  People writing in comp.arch
<have suggested that this is somewhat optimistic.

You can get 60 Mflops, if

	The pipeline instrutions are used.
	All data is on-chip (cache, registers).
	The loop consists of exactly 2 FP adds and 1 FP multiply.
	The loop is unrolled twice.
	All outputs are fed back into the pipeline.
	No more than one input comes from cache.

This is the quoted rate "guaranteed not to exceed".

--
Alan E. Klietz
Minnesota Supercomputer Center, Inc.
1200 Washington Avenue South
Minneapolis, MN  55415
Ph: +1 612 626 1737	       Internet: alan@msc.edu