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From: rstewart@megatek.UUCP (Rich Stewart)
Newsgroups: comp.arch
Subject: Re: i860 MFLOP rate?
Message-ID: <799@cvxmb3.megatek.uucp>
Date: 30 Oct 90 18:15:58 GMT
References: <9010291839.AA07178@lilac.berkeley.edu>
Organization: Megatek Corporation, San Diego, California
Lines: 25

In article <9010291839.AA07178@lilac.berkeley.edu> rmbult01@ulkyvx.BITNET (Robert M. Bultman) writes:
>The i860 has been quoted as having a peak MFLOP rate of ~150
>MFLOPS.  (This is more of a guess.)  People writing in comp.arch
>have suggested that this is somewhat optimistic.  Without causing
>arguments about what constitutes an "average" or "typical" load
>on a processor, I would like to ask the question, "What is the


for a 40 meg. part:

The peak is 80 MFLOP.
If you are using a compiler to generate your code, expect 3 clocks/ floating
point instruction, so 13 MFLOP

If you are writing assembly, it all depends on the problem you
are trying to solve.  The chip does real well with matrix ops, you may
get close to 80 MFLOP. But there are common situations where you may not 
exceed 13 MFLOP.

-Rich

rstewart@megatek.uucp


My opinions are just that.