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From: apfiffer@admin.cse.ogi.edu (Andy Pfiffer)
Newsgroups: comp.arch
Subject: Re: i860 MFLOP rate?
Message-ID: <13439@ogicse.ogi.edu>
Date: 31 Oct 90 08:32:10 GMT
References: <9010291839.AA07178@lilac.berkeley.edu> <799@cvxmb3.megatek.uucp>
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>In article <9010291839.AA07178@lilac.berkeley.edu> rmbult01@ulkyvx.BITNET (Robert M. Bultman) writes:
>The i860 has been quoted as having a peak MFLOP rate of ~150
>MFLOPS.  (This is more of a guess.)  People writing in comp.arch
>have suggested that this is somewhat optimistic.

Guaranteed Not To Exceed MFLOPS on i860's are in the neighborhood of
two times the clock rate.  That is based on performing an FP add and an
FP multiply concurrently.

Hand-tuned assembly can approach this, provided you understand the details
of a given platform's memory system (page-mode, external pipeline depth, etc.).

Good compilers are now available from the Portland Group. Their compiler
loves long, tight loops that pipeline well and I've seen firsthand just
over 20 SP MFLOPS @ 33MHz on one loop in sample dusty-deck Fortran from
a customer; but that is not typical (4 to 12 is more often observed).

Compiler playthings and brain-damaged, orphaned development systems are
available from Intel (please don't get me started on a Star860 tirade...).


The i860 exception handler didn't cause premature grey *on* my head, but
I did notice the hair turning grey as it fell *off* my head.


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Andy Pfiffer			apfiffer@admin.ogi.edu
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