Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!husc6!encore!jcallen
From: jcallen@Encore.COM (Jerry Callen)
Newsgroups: comp.arch
Subject: Smart I-cache?
Summary: It's been done...
Message-ID: <13120@encore.Encore.COM>
Date: 1 Nov 90 15:58:43 GMT
Reply-To: jcallen@encore.Com (Jerry Callen)
Organization: Encore Computer Corp, Marlboro, MA
Lines: 19

davidsen@crdos1.crd.ge.com (bill davidsen) writes:

>  The feature is intelligent I-cache, which only stores instructions
>which are the target of jumps.

This is, of course, the AMD29K branch target cache, which stores the
target of the branch and the next 3 instructions. The idea is that 
this gives the memory system 4 clock ticks in which to deliver the
4th instruction after the branch target, and then hopefully the memory
system can deliver subsequent instructions every cycle (page mode DRAM,
for instance).

I attended an AMD marketing pitch a few years ago on the 29K; the
argument was that the branch target cache enables the 29K to squeeze
reasonable performance out of a cheap DRAM memory system. Can anyone
comment on how effective the branch target cache is?

-- Jerry Callen
   jcallen@encore.com