Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!husc6!unix!morgan
From: morgan@unix.SRI.COM (Morgan Kaufmann)
Newsgroups: comp.arch
Subject: Re: intro text suggestions
Message-ID: <17810@unix.SRI.COM>
Date: 2 Nov 90 05:08:46 GMT
References: <1990Oct29.225043.2425@cs.columbia.edu>
Reply-To: morgan@unix.sri.com (Morgan Kaufmann)
Organization: SRI International, Menlo Park, CA
Lines: 73

In article <1990Oct29.225043.2425@cs.columbia.edu> wolberg@cs.columbia.edu (George Wolberg) writes:
>I'm looking for a good textbook that provides a thorough, comprehensive,
>and up-to-date introductory treatment of computer architecture. The book
>is intended for use by undergraduates. Any and all suggestions are welcomed.
>Comments about the primary strengths and weaknesses of the texts would be
>especially appreciated. Please reply to wolberg@cs.columbia.edu
>
>Thanks a lot,
>George Wolberg
>-- 
>----------------------------------------------------------------------
>George Wolberg				Department of Computer Science
>wolberg@cs.columbia.edu			Columbia University



For those who have been following these postings the exact title is:

COMPUTER ARCHITECTURE:  A QUANTITATIVE APPROACH, by John Hennessy
(Stanford) and Dave Patterson (UC Berkeley).


This book is available through technical bookstores, and should be
in-stock at the larger stores in major cities.  It can also be ordered
directly from the publisher:

Morgan Kaufmann Publishers,
2929 Campus Drive, Ste 260,
San Mateo, CA 94403,
USA

Tel 800/745-READ (US AND CANADA), 415/578-9911 (ELSEWHERE)
FAX 415/578-0672
Email morgan@unix.sri.com
 
VISA, Mastercard, personal checks and money orders will be accepted.
The cost of the title is $54.95 plus $3.50 shipping/handling for
each copy ordered for US and Canadian shipment and $6.50 for shipment
to all other territories.  California residents please add appropriate
sales tax.


Contents: 

1. Fundamentals of Computer Design.
2. Performance & Cost. 
3. Instruction Set Design:  Alternatives and Principles.
4. Instruction Set Examples and Measurements of Use.
5. Basic Processor Implementation Techniques.
6. Pipelining.
7. Vector Processors.
8. Memory Hierarchy Design.
9. Input/Output.
10. Future Directions & Parallel Computation.
Appendices: 
A) Computer Arithmetic, by David Goldberg (Xerox PARC)
B) Complete Instruction Set Tables (VAX, 360, 8086)
C) Detailed Instruction Set Measurements (VAX, 360, 8086, DLX)
D) Time Versus Frequency Measurements
   (VAX 11/780, IBM 370/168, 8086 in an IBM PC, DLX)
E) Survey of RISC Architectures
   (DLX, i860, MIPS, M88000, SPARC).

Another title of interest that expands upon performance issues for
cache and memory hierarchies also from Morgan Kaufmann:

CACHE & MEMORY HIERARCHY DESIGN:  A PERFORMANCE DIRECTED APPROACH,
by Steven A. Przybylski (MIPS), $33.95
Contents:  Intro.  Background Material.  The Cache Design Problem
and its Solution.  Performance Directed Cache Design.  Multi-Level
Cache Hierarchies.  Summary, Implications and Conclusions. 
Appendices:  A) Validation of Empirical Results, B) Modeling Write
Strategy Effects.