Path: utzoo!attcan!uunet!midway!ncar!zaphod.mps.ohio-state.edu!rpi!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: Smart I-cache?
Message-ID: <2831@crdos1.crd.ge.COM>
Date: 2 Nov 90 14:04:33 GMT
References: <13120@encore.Encore.COM>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
Lines: 17

In article <13120@encore.Encore.COM> jcallen@encore.Com (Jerry Callen) writes:

| I attended an AMD marketing pitch a few years ago on the 29K; the
| argument was that the branch target cache enables the 29K to squeeze
| reasonable performance out of a cheap DRAM memory system. Can anyone
| comment on how effective the branch target cache is?

  A number of people have pointed out that a branch target cache makes
really good use of the cache in terms of keeping the CPU busy, but is
less effective in reducing main memory loading.

  I could be easily convinced that a small branch target cache, like 4k
or so, and a larger general cache for both I and D would be desirable.
Then you get into delays caused by multilevel cache...
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
      The Twin Peaks Halloween costume: stark naked in a body bag