Path: utzoo!attcan!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.lang.misc
Subject: Re: Re: Aggressive optimization
Message-ID: <8538@scolex.sco.COM>
Date: 2 Nov 90 08:36:49 GMT
References: <2301@wn1.sci.kun.nl> <8960020@hpfcso.HP.COM>
Sender: news@sco.COM
Reply-To: seanf (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 29


In article <8960020@hpfcso.HP.COM> mjs@hpfcso.HP.COM (Marc Sabatella) writes:
>None of these transformations violate the cardinal rule of assemblers, namely
>that of providing a one-to-one translation.  

The MIPS assembler does, I believe, provide a one-to-one translation.
However, it may also stick in NOP's, as necessary.

Remember that the original MIPS chip did not have "interlocks":  if you used
a register before the previous instruction was done with it, you would get
wrong results.  The NOP's were necessary at that point.

Consider a machine like the CDC 170-state architecture (any comp.arch
readers who knew I would bring it up somehow? 8-)).  It has/had 60-bit
words, with 15 and 30 bit instructions.  The assembler would pack 1-4
instructions per word; it provided padding (nop's, essentially) when the
next instruction wouldn't fit (e.g., 15 / 30 / 30 won't fit in one word), or
when the instruciton was proceeded directly by a lable (since you couldn't
jump into the middle of a word).

That was about as much a rewriting as the MIPS assembler (albeit on a
smaller scale 8-)), yet it was still an assembler.

-- 
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Sean Eric Fagan  | "Quoth the raven,"
seanf@sco.COM    | "Eat my shorts!"
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(408) 458-1422   | Any opinions expressed are my own, not my employers'.