Path: utzoo!attcan!uunet!crdgw1!rpi!zaphod.mps.ohio-state.edu!usc!elroy.jpl.nasa.gov!turnkey!orchard.la.locus.com!fafnir.la.locus.com!snap.la.locus.com!dlt From: dlt@locus.com (Dan Taylor) Newsgroups: comp.sys.amiga.hardware Subject: Re: Blitter Speed(?) Message-ID: Date: 24 Oct 90 23:03:13 GMT References: <1990Oct22.195001.28782@idt.unit.no> <15343@cbmvax.commodore.com> Organization: Locus Computing Corporation, Los Angeles, California Lines: 44 daveh@cbmvax.commodore.com (Dave Haynie) writes: >In article <1990Oct22.195001.28782@idt.unit.no> daglem@solan7.solan.unit.no (Dag Lem) writes: >>Would it be theoretically possible to make new custom chips that run at, say, >>28MHz cycles, and to make the chip-RAM follow this speed? >Here we go again... What, exactly, do you mean by "28MHz speed". One cycle >every clock period? Every two clock periods, like the 68030? Every three, >like the 68020? Every four, like the 68000? I'll bite. How about using burst access to 32-bit ram interleaved with the 680[34]0 burst cycles? So, we get 4 accesses in 4 (or 5) clocks, and we can use at least a 28+ MHz clock, for PAL/NTSC compatibility. Although, as long as raster fetch DMA is faster than the desired bit rate, it doesn't HAVE to be synchronous. Anyway, with a doubled bus width, and 4 times as many accesses per second (7.19 MHz 2 clocks/access vs. 28.8 MHz 8 clocks/ 4 accesses - both sharing with the processor 50%), we could easily support additional bit-planes, increased coprocessor access, or both. >DRAM can't easily support that kind of speed See above. We can access RAM for DMA as fast as the CPU, only half as often, if the CPU is also accessing chip RAM just then. Remember, some CHIP items, like the floppies, won't require proportionally more access, so their extra slots would be free. >Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" > {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy > Standing on the shoulders of giants leaves me cold -REM I WANT those cycles. Please, please, make me an Amiga with a 68040, 32-bit interleaved burst access CHIP RAM (run the SCSI that way, too), so I can have 1280x960, 4-plane for engineering/scientific duties, 720x480 (NTSC) interlaced 24-plane (or maybe a 12-plane super-HAM) for video work, and 640x400 non-interlaced 8-plane for SUPER games (excellent blitter access). Yes, I'd pay the extra $1000 (+monitor) over an A3000. How do I come up with this number? FAST RAM vs CHIP RAM on the A3000, 68040 2nd quarter 1991 vs 68030 3rd quarter 1990, less silicon in the custom chip set, and HIGHER sales projections, 'specially with SYS V.4. -- * Dan Taylor * The opinions expressed are my own, and in no way * * dlt@locus.com * reflect those of Locus Computing Corporation. *