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From: lkoop@pnet01.cts.com (Lamonte Koop)
Newsgroups: comp.sys.amiga.hardware
Subject: A2630 Faster RAM?
Message-ID: <5329@crash.cts.com>
Date: 29 Oct 90 07:36:10 GMT
Sender: root@crash.cts.com
Organization: People-Net [pnet01], El Cajon CA
Lines: 16

I have a question about the A2630 030 accelerator.  It's fairly well known
that replacing the standard 100ns DRAMs on the board with 80ns RAM will allow
the board to run somewhat faster.  Here's the question: HOW?  The A2630 uses a
3 wait state design...what control logic determines if it can run faster?
[I realize a 680x0 memory access is an assertion of Address Strobe on the bus,
with the cpu placing the address on the address lines, and the memory device
returning DTACK (or with an 030 or 020, DSACK0 and DSACK1 to accommodate
different port size activity), but could someone (Dave?) kindly explain waht
exactly is allowing that faster speed access [something just doesn't seem to
fit here]) Many thanks in advance.
 
--LaMonte

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