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From: aduncan@rhea.trl.oz (Allan Duncan)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: RISC Amiga
Message-ID: <2425@trlluna.trl.oz>
Date: 31 Oct 90 21:38:55 GMT
References: <1990Oct30.192213.12708@Neon.Stanford.EDU>
Sender: news@trlluna.trl.oz
Lines: 21

From article <1990Oct30.192213.12708@Neon.Stanford.EDU>, by torrie@Neon.Stanford.EDU (Evan James Torrie):
>>On the other hand, the 68040 is as fast as current-generation RISC
>>chips.  So why go RISC at all?
> 
>   Because next year's implementation of RISC (the 88110) will be about
> two to three times faster than next year's implementation of the 68040
> (even with the 040 running at 50MHz)

When you configure in memory at prices we in the street can afford (ie
dynamic ram) riscs stop dead, as their high mip speed is derived from
memory fetching on every cycle, whereas a cisc spends some time decoding
giving the memory time to catch its breath.  With sensible memory
interfacing (and you don't get anything else these days at these speeds)
the effective computation you get is a function of memory bandwidth, not
cisc/risc.  Split instruction/data paths and dual ported data memory are
probably the way of the future, but not at the cheap end of the market.
Wider buses too.
Allan Duncan	ACSnet	a.duncan@trl.oz
(03) 541 6708	ARPA	a.duncan%trl.oz.au@uunet.uu.net
		UUCP	{uunet,hplabs,ukc}!munnari!trl.oz!a.duncan
Telecom Research Labs, PO Box 249, Clayton, Victoria, 3168, Australia.