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From: jdickson@jato.jpl.nasa.gov (Jeff Dickson)
Newsgroups: comp.sys.amiga.tech,comp.sys.amiga.hardware
Subject: Re: RISC Amiga and multiprocessing
Message-ID: <1990Nov2.190352.5801@jato.jpl.nasa.gov>
Date: 2 Nov 90 19:03:52 GMT
References: <1990Nov2.070729.19128@engin.umich.edu>
Reply-To: jdickson@jato.Jpl.Nasa.Gov (Jeff Dickson)
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Newsgroups: comp.sys.amiga.tech,comp.sys.amiga.hardware
Subject: Re: RISC Amiga and multiprocessing
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References: <1990Nov2.070729.19128@engin.umich.edu>
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	This is merely speculation. I find it difficult to believe that 
CBM could one day dump Motorola CPU's and take on say Intel's. What
leads me to this speculation are the major differences in Motorola's and
Intel's bus philosophy. For one, Motorola goes for memory mapped I/O while
Intel goes for non memory mapped I/O. Another, Motorola has a more robust
bus handshaking protocol. Motorola CPU's say "here it is" and the type of
bus cycle lasts until whoever got it says "OK. I got it". Intel CPU's
say "Go for it" and its up to who ever it is for to assert wait cycles if
more time is needed. I also believe there are big differences in interupts
and interupt levels. Seems that gearing the Amiga for a non Motorola CPU
at this time, would involve a major overhaul. Please execuse my ignorance
in this matter if I am partially mistaken. The above argument was valid
for some older CPUs - believe it still is.
 

					Jeff
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Jeff S. Dickson                              jdickson@zook.jpl.nasa.gov