Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!usc!ucsd!nosc!crash!pro-sol.cts.com!mdavis
From: mdavis@pro-sol.cts.com (Morgan Davis)
Newsgroups: comp.sys.apple2
Subject: Re: Proposal: Apple II+ 60Hz Timing Signal
Message-ID: <5399@crash.cts.com>
Date: 1 Nov 90 17:36:10 GMT
Sender: root@crash.cts.com
Lines: 30

unknown@ucscb.UCSC.EDU (The Unknown User) writes:

} Why is there a 60 Hz signal coming out of a 4 bit binary counter?

Got me.  I really can't answer that.  There just is.  The four chips from
D-11 to D-14 appear to be dividing an incoming signal that starts out at
60Hz.  Where that actual source is, I don't know.  I just know which pin
I can read that lets me access that signal.

} Could you tell me if they're most significant bit 0 or least
} significant bit 0? (What I'm looking in is the Motorola FAST and LS TTL data
} book)

That I don't know either.  I'm a software guy, not a hardware guy.

} Just trying to understand how you know that that is a 60Hz
} signal coming out and "where it's coming from"...

Magic.  I read a tip here about creating roughly 59.xx Hz interrupts on
the II+ by taking a wire from pin #11 of D-11 to the CPU's interrupt
request line.  I deduced that it must be some sort of near 60Hz signal
(it doesn't have a 50% duty cycle, BTW).  I figured if I routed that signal
to an input I could poll it from software.  The cassette port input seemed
to be the best choice since it is not used much (if at all) these days.

--Morgan

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