Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!jarthur!nntp-server.caltech.edu!toddpw
From: toddpw@nntp-server.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: Proposal: Apple II+ 60Hz Timing Signal
Message-ID: <1990Nov2.075932.29291@nntp-server.caltech.edu>
Date: 2 Nov 90 07:59:32 GMT
References: <5399@crash.cts.com>
Organization: California Institute of Technology, Pasadena
Lines: 27

>unknown@ucscb.UCSC.EDU (The Unknown User) writes:

>} Why is there a 60 Hz signal coming out of a 4 bit binary counter?

D11-D14 in the ][+ are all 4 bit binary counters. They generate the video
counter. The Mega II allows you to read the exact value of the counter at
C02E and C02F, but that counter started out as four little TTL chips wired
in an ingenious way. Pin #11 of D11 happens to be V5, a.k.a. the hi bit
of C02E in the GS. It goes high for six scan lines at the end of VBL.
Since it has the same period as VBL, it is therefore a 60 Hz signal.

>} Could you tell me if they're most significant bit 0 or least
>} significant bit 0? (What I'm looking in is the Motorola FAST and LS TTL data
>} book)

TTL counters label the least significant bit 0. For the 161 that's pin 14.
Pin 11 is the hi bit of the 4 bit counter.

>} Just trying to understand how you know that that is a 60Hz
>} signal coming out and "where it's coming from"...

Can't speak for Mr. Davis, but I've got an Apple ][ reference manual and a IIgs
technote to back me up. The 60 hz signal is essentially the top bit of the
counter that provides the video address to the rest of the computer.

Todd Whitesel
toddpw @ tybalt.caltech.edu