Path: utzoo!attcan!uunet!ogicse!mintaka!bloom-beacon!vaxeline!gordon
From: gordon@vaxeline.COM (Gordon Lee)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: 8250 and 8259 chips
Keywords: 8250 8259 interrupts serial
Message-ID: <1210@vaxeline.COM>
Date: 29 Oct 90 20:15:24 GMT
Reply-To: gordon@ftp.com (Gordon Lee)
Organization: FTP Software, Inc.
Lines: 43

I have encountered some ambiguity in the IBM AT Tech Ref concerning the 
interaction between the 8250 and 8259 PIC chip.  The 8250 generates four
types of interrupt, namely: Modem Status, Receive, Transmit Completion, 
and Line Status.  To service an interrupt, the interrupt handling routine
must read the Interrupt Identification Register (IIR) to demux on the type 
of interrupt.  This much is fairly clear.

My Interrupt Service Routine (ISR) is currently defficient in that it 
can miss a transmit completion, thereby wedging my outgoing data stream.  
This only happens under heavy bidirectional traffic, which leads me to 
believe that my ISR is losing when a transmit completion intr and a receive 
intr happen "simultaneously".  I think my routine is handling the receive
interrupt while allowing the transmit completion interrupt to drop on 
the floor.

Under a description of the IIR, the Tech Ref says: "When the IIR is 
addressed, the pending interrupt with the highest priority is held 
and no other interrupts are acknowledged until the microprocessor 
services that interrupt."  I interpret that as follows:  
	- more than one interrupt type can be pending at once
	- of the interrupts pending, the IIR returns that which
		has the highest priority, and occured before any 
		other interrupts of the same type
What I have not been able to determine, is exactly what condition/state 
constitutes "(when the) microprocessor services that interrupt".  I also
cannot determine what my issuing a specific EOI to the PIC will do to the 
state of the machine.  And above all, I cannot determine how interrupts
of other types are dealt with while my ISR is executing.

The crux of what I need to know and what the manual doesn't want
to tell me is:  how to cleanly service a single physical interrupt
which is signalling the occurence of more than one type of UART 
interrupt condition.  I also need to know how to expect a subsequent
interrupt while I am in my service routine, and the proper way to 
acknowledge to the PIC notification of multiple "simultaneous" interrupts.

Any advice or pointers would be much appreciated.

-- 
==========================================================================
Gordon Lee
Member, Technical Staff
FTP Software, Inc.   (617) 246-0900 x287