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From: seth@miro.Berkeley.EDU (Seth Teller)
Newsgroups: comp.sys.sgi
Subject: Re: c-shells inside makefiles
Message-ID: <29272@pasteur.Berkeley.EDU>
Date: 27 Oct 90 03:20:39 GMT
References: <28936@pasteur.Berkeley.EDU> <1990Oct23.055715.6973@foetus.syd.sgi.oz.au>
Sender: news@pasteur.Berkeley.EDU
Reply-To: seth@miro.Berkeley.EDU (Seth Teller)
Organization: University of California at Berkeley
Lines: 41

In article <meaningless #'s>, peterk@foetus.syd.sgi.oz.au (Peter Kerney) wrote:
>The problems is not ussimply using shells in Makefiles. The problem is
>using 'csh' (THE C-SHELL) from within a Makefile.
>The example you gave was a Bourne shell.
>The makefile I want to work is one that uses the C-shell. (I like it better.)
>Here is a simple test that i[f] anyone                    [^^^^^^^^^^^^^^^^!]
>can get to work I would love it.
>all:
>	foreach i (1 2)
>		echo $i
>	end
>If you can get this to work, everything else is possible.
>Peter Kerney. Silicon Graphics, Sydney, Australia. (peterk@syd.sgi.oz.au)

well, you certainly have unimpeachable reasons for preferring the c shell.
here's a makefile embedding of c shell code that's sort of cheating, but
it does work:

SHELL=/bin/csh
EXECUTE=/bin/sed -e 's/@/$$/g' | /bin/csh

loop:
	echo "foreach i (1 2)\
	echo @i \
	end" | $(EXECUTE)

the tricky part is dealing with "$"s and newlines.  the code has to 
be all on one line (for make) but separated into different lines
(for csh).  so... the idea is to use '@' (or any other odd character
of your choice) in place of $, then substitute for it, using sed,
after make's parsing.  note that the SHELL macro is necessary, since
without it the command text gets collapsed onto a single line.
the $$ escapes the second $ from make's conversion, as noted in
the man page.

finally, it's cheating because the /bin/csh is invoked explicitly
by make, not implicitly.  i'd be interested in other solutions, too.

have fun.

seth