Newsgroups: sci.electronics
Path: utzoo!henry
From: henry@zoo.toronto.edu (Henry Spencer)
Subject: Re: Refreshing DRAM
Message-ID: <1990Oct26.164132.28594@zoo.toronto.edu>
Organization: U of Toronto Zoology
References: <44900017@uxa.cso.uiuc.edu>
Date: Fri, 26 Oct 90 16:41:32 GMT

In article <44900017@uxa.cso.uiuc.edu> smlg1015@uxa.cso.uiuc.edu writes:
>... If one increases the amount of DRAM by a factor of
>4, say, does this mean that the microprocessor spends 4 times as much time
>refreshing, and hence, less time executing useful instructions? Does refreshing
>occur chip by chip, or all DRAMS chips simultaneously? ...

In sensible designs, memory refresh is simultaneous over the whole array.
Also, in general it is done by independent hardware, with the processor
not involved, although the result may be occasional slight delays in
processor memory accesses.
-- 
The type syntax for C is essentially   | Henry Spencer at U of Toronto Zoology
unparsable.             --Rob Pike     |  henry@zoo.toronto.edu   utzoo!henry