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From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: The CPU with 3 brains
Message-ID: <42737@mips.mips.COM>
Date: 3 Nov 90 22:46:12 GMT
Sender: news@mips.COM
Reply-To: mark@mips.COM (Mark G. Johnson)
Organization: MIPS Computer Systems, Inc.
Lines: 56

Sometimes RISC evangelists will tell you is that if you choose a
simplified instruction set, you can build a fast CPU, using relatively
little hardware, on an aggressive schedule.  That's why, (they say), the
first CPU chips in newly-available semiconductor technologies are likely
to be RISCs.  For example, the first 32b uP's in Gallium Arsenide were
RISCs -- it was a good way to quickly crank out a fast machine while
staying within a constrained gate-budget, at a time when VLSI GaAs was
still slightly out-of-reach.  {Disclaimer: occasionally, I propound
these views myself.}

RISCs, even 32-bit ones, were simple: the Acorn ARM is about 10K gates,
the Fujitsu SPARC is 20K gates + register file, the first MIPS ("R2000")
is 110K transistors {about 30K gates}, and the MC88000's integer CPU
was small enough that, even in the first implementation, there was
enough room on the chip to include floating point hardware.  Call it
30K gates for the 88000's integer CPU.

Now, perhaps, today's world is different.  Lots of ASIC vendors are
glad to sell you sea-of-gates gate arrays which contain well over
100,000 usable gates.  These are available in CMOS, BiCMOS, BiCMOS-ECL,
and recently, Gallium Arsenide.  If you're willing to limit your options
to straight CMOS, the number is closer to 200K usable, wireable gates.

A little bit of trivial finger-counting reveals that 100K+ gates is
enough to do something potentially interesting.  Therefore I put
forward the idea that a multiple-CPU-on-the-same-chip processor is
now feasible, practical, and (controversy coming:) useful.  How about
spending the gate budget as follows:

       SPARC CPU:   30K gates   }     all of these reside on the
       MIPS CPU:    30K gates   }     same die, a 100K gate array
       i286 CPU:    30K gates   }     in BiCMOS technology

If this chip were finished, complete, debugged, and available today,
imagine the cool things you could do with it.  Also imagine the
Budzillions of dollars' worth of software already written for your
machine.  Also imagine the frolic and fun of porting the O/S's and
other system software onto this three-brained, schizophrenic machine.
"An excellent source of thesis topics," as they say at 6100 Main in
Houston.

Of course you could pick other CPUs if you like; the slick thing is
that the reduced instruction set ones enable you to slap several of
em on the same die and still have room "left over" for a 286, a Z80,
and a couple of 6502's.  How about a 200Kgate CMOS array having an
Am29000, a CRISP, 2 Transputers, an 88k, and a 286?  Or how about
6 SPARCs and MMUs on the same chip?

Given the obvious desirability and superiority of this idea :-),
why are some folks instead using millions of gates, spread across
several chips, to implement a single CPU (e.g. NexGen, Metaflow,
SpEc, Edge)?  :-)
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
	(408) 524-8308    mark@mips.com  {or ...!decwrl!mips!mark}