Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!uunet!know!zaphod.mps.ohio-state.edu!julius.cs.uiuc.edu!apple!amdcad!mozart.amd.com!proton!tim
From: tim@proton.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Smart I-cache?
Message-ID: <1990Nov3.202916.18265@mozart.amd.com>
Date: 3 Nov 90 20:29:16 GMT
References: <13120@encore.Encore.COM>
Sender: usenet@mozart.amd.com (Usenet News)
Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc., Austin, Texas
Lines: 13

In article <13120@encore.Encore.COM> jcallen@encore.Com (Jerry Callen) writes:
| I attended an AMD marketing pitch a few years ago on the 29K; the
| argument was that the branch target cache enables the 29K to squeeze
| reasonable performance out of a cheap DRAM memory system. Can anyone
| comment on how effective the branch target cache is?

Mark Hill's thesis compared a number of different caches, including
the 29K's BTC.  He concluded that the BTC was more effective than a
regular cache up to about 2K bytes.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)