Newsgroups: comp.arch
Path: utzoo!henry
From: henry@zoo.toronto.edu (Henry Spencer)
Subject: Re: The CPU with 3 brains
Message-ID: <1990Nov4.014901.23819@zoo.toronto.edu>
Organization: U of Toronto Zoology
References: <42737@mips.mips.COM>
Date: Sun, 4 Nov 90 01:49:01 GMT

In article <42737@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>spending the gate budget as follows:
>
>       SPARC CPU:   30K gates   }     all of these reside on the
>       MIPS CPU:    30K gates   }     same die, a 100K gate array
>       i286 CPU:    30K gates   }     in BiCMOS technology

Actually, I suggested something like this quite a while ago, when some
Intel bigshot had mumbled in public about soon being able to put four
CPUs on a single chip and what can we possibly do with it all.  If you're
Intel, it's obvious:  one 860, one 486, one 80960, and fill up the last
slot with odds and ends like 8080, 8008, 4004, 2920, etc.  Then you at
last have compatibility among Intel CPUs:  one chip runs software for
any of them!
-- 
"I don't *want* to be normal!"         | Henry Spencer at U of Toronto Zoology
"Not to worry."                        |  henry@zoo.toronto.edu   utzoo!henry