Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!mcsun!ukc!dcl-cs!aber-cs!athene!pcg From: pcg@cs.aber.ac.uk (Piercarlo Grandi) Newsgroups: comp.arch Subject: Re: The CPU with 3 brains Message-ID: Date: 4 Nov 90 18:31:57 GMT References: <42737@mips.mips.COM> Sender: pcg@aber-cs.UUCP Organization: Coleg Prifysgol Cymru Lines: 68 In-reply-to: mark@mips.COM's message of 3 Nov 90 22:46:12 GMT On 3 Nov 90 22:46:12 GMT, mark@mips.COM (Mark G. Johnson) said, somwhat tongue in cheek: mark> Sometimes RISC evangelists will tell you [ ... that RISC CPUs need mark> ridiculously low gate counts, 10k to 30k and that this means that mark> one can build RISC cpus with very advanced, low density mark> technologies ... ] Note that the gate counts of some non RISC chips were also low; the original 68k, the 286, the Z8000. mark> Now, perhaps, today's world is different. Lots of ASIC vendors are mark> glad to sell you sea-of-gates gate arrays which contain well over mark> 100,000 usable gates. mark> A little bit of trivial finger-counting reveals that 100K+ gates is mark> enough to do something potentially interesting. Therefore I put mark> forward the idea that a multiple-CPU-on-the-same-chip processor is mark> now feasible, practical, and (controversy coming:) useful. Ahem. This was the subject of some of my earlier postings: why not have multiple RISC CPUs on a chip instead of a single superscalar one. Nobody bothered to reply... Sigh sigh... But now you add a perverse twist to this idea: mark> How about spending the gate budget as follows: mark> SPARC CPU: 30K gates } all of these reside on the mark> MIPS CPU: 30K gates } same die, a 100K gate array mark> i286 CPU: 30K gates } in BiCMOS technology mark> If this chip were finished, complete, debugged, and available mark> today, imagine the cool things you could do with it. Also imagine mark> [ ... other similar perversions ... ] Your idea is crazy, but not crazy enough to be marketable :-). Given that the main attraction of the greatest commercial successes in computer architecture, the 370 and 80x86 lines, is protection of software investment, I think that the best idea would not be to have a chip with multiple RISC souls, because the RISC instruction sets are too recent and too few dusty decks run on them. What about a chip with the 1100, 6000, 370, 6502, 8080, 80286, 68000, instruction sets on it? I don't think that a simple implementation (with some instructions trapped) of any of these would take a lot of gates. mark> Given the obvious desirability and superiority of this idea :-), mark> why are some folks instead using millions of gates, spread across mark> several chips, to implement a single CPU (e.g. NexGen, Metaflow, mark> SpEc, Edge)? :-) Now let's instead switch to very serious mode: What about the IBM RS/6000 that is a 3-4-5 way superscalar and takes 6 million transistors and is not ROMP compatible? Are superscalable instruction sets necessarily different from currently existing ones? Do you need millions of transistors to build a superscalar? Again, is it better to spend a large transistor budget on a superscalar CPU, with a new, superscalar oriented instruction set, or on multiple CPUs on a chip with an existing RISC instruction set? -- Piercarlo "Peter" Grandi | ARPA: pcg%uk.ac.aber.cs@nsfnet-relay.ac.uk Dept of CS, UCW Aberystwyth | UUCP: ...!mcsun!ukc!aber-cs!pcg Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@cs.aber.ac.uk