Path: utzoo!attcan!uunet!zaphod.mps.ohio-state.edu!swrinde!ucsd!ucbvax!bloom-beacon!math.mit.edu!drw
From: drw@laurent.mit.edu (Dale R. Worley)
Newsgroups: comp.arch
Subject: Strange cache addressing algorithm
Message-ID: <DRW.90Nov6011452@laurent.mit.edu>
Date: 6 Nov 90 09:14:52 GMT
Sender: daemon@athena.mit.edu (Mr Background)
Organization: MIT Dept. of Tetrapilotomy, Cambridge, MA, USA
Lines: 13

The Intel i860 uses a strange algorithm for deciding which line in the
cache to assign a particular memory address.

I remember reading an article in the last year or so that argued that
the usual low-n-bits-of-the-address algorithm was susceptible to bad
performance (especially if you referenced only every n-th byte of
memory) and discussed a hashing (?) algorithm for assigning cache
lines to addresses.  Does anybody remember where this was published?

Thanks,

Dale
drw@math.mit.edu